Please solve in details and in a clear way. D 8.106 The two-stage CMOS op amp in Fig. P8.106 is...

Please solve in details and in a clear way.
D 8.106 The two-stage CMOS op amp in Fig. P8.106 is fabricated in a 0.18-um technology having 4 kp tp (a) With A and B grounded, perform a dc design that will result in each of Q,, Q2, Qs, and Q, conducting a drain current of 100 uA and each of Q% and Q a current of 200 HA. Design so that all transistors operate at 0.2-V overdrive voltages. Specify the WIL ratio required for each MOSFET. Present your results in tabular form. What is the dc voltage at the output (ideally)? (b) Find the input common-mode range. (c) Find the allowable range of the output voltage. (d) With v V2 and vvl2, find the voltage gain v/v. Assume an Early voltage of 6 V. VDD 0.9 v 03 24 IREF 200 μΑ 26 25 Qs Q, ks =-0.9 V Figure P8.106 D 8.106 The two-stage CMOS op amp in Fig. P8.106 is fabricated in a 0.18-um technology having 4 kp tp (a) With A and B grounded, perform a dc design that will result in each of Q,, Q2, Qs, and Q, conducting a drain current of 100 uA and each of Q% and Q a current of 200 HA. Design so that all transistors operate at 0.2-V overdrive voltages. Specify the WIL ratio required for each MOSFET. Present your results in tabular form. What is the dc voltage at the output (ideally)? (b) Find the input common-mode range. (c) Find the allowable range of the output voltage. (d) With v V2 and vvl2, find the voltage gain v/v. Assume an Early voltage of 6 V.
VDD 0.9 v 03 24 IREF 200 μΑ 26 25 Qs Q, ks =-0.9 V Figure P8.106