1. Consider the following current mirror combination, where all transistors have the same...

1. Consider the following current mirror combination, where all transistors have the same kn'(W/L) = kp'(W/L) = 2mA/V2, and VTN-1У, VTP–1V. It is also given that VDD1-10V, VDD2-8V. Remember that for saturation the drain current is given by IDー½ k,”(W/L) (VGS-Yn)” for NMOS and ID ½ kp”(WL) (VGS-V,»)2 for PMOS. You can ignore the channel modulation for all transistors. (a) Find the value of R so that I.-1mA. (b) Are transistors Q1, Q2, Q3 in saturation? (c) What is the range of Vo so that Q4 is in saturation? (d) Assume that a resistor 1K is connected to the output node (at Vo) as the load (i.e. one terminal of the resistor is connected to the output node, and the other to the ground). Will the particular current mirror support this load? (e) Assume that a resistor 1K in series to a constant voltage source Vx are connected to the output node (at Vo) as the load (i.e. one terminal of the resistor is connected to the output node and the other to the voltage course. The other voltage source terminal is connected to the ground). What is the allowable voltage range for V? REF 0 V. 0 1. Consider the following current mirror combination, where all transistors have the same kn'(W/L) = kp'(W/L) = 2mA/V2, and VTN-1У, VTP–1V. It is also given that VDD1-10V, VDD2-8V. Remember that for saturation the drain current is given by IDー½ k,”(W/L) (VGS-Yn)” for NMOS and ID ½ kp”(WL) (VGS-V,»)2 for PMOS. You can ignore the channel modulation for all transistors. (a) Find the value of R so that I.-1mA. (b) Are transistors Q1, Q2, Q3 in saturation? (c) What is the range of Vo so that Q4 is in saturation? (d) Assume that a resistor 1K is connected to the output node (at Vo) as the load (i.e. one terminal of the resistor is connected to the output node, and the other to the ground). Will the particular current mirror support this load? (e) Assume that a resistor 1K in series to a constant voltage source Vx are connected to the output node (at Vo) as the load (i.e. one terminal of the resistor is connected to the output node and the other to the voltage course. The other voltage source terminal is connected to the ground). What is the allowable voltage range for V? REF 0 V. 0